( / 6) mitsubishi 0107 M62354AGP 8bit 6ch d-a converter with buffer amplifiers 1 description m62354a is a cmos structured semiconductor integrated ciruict integrating 6 channels of built-in d-a converters with high performance buffer operational amplifier for each channel output. 3-wire serial interface (di,clk,ld) method is used for the taransfer format of digital data to allow connection with microcomputer with minimum wiring do terminal is provided to allow cascading serial use. built-in buffer operational amplifiers are designed to operate or full-swing in the whole voltage range from vcc to gnd for each input/output. and their higher stability for capacitive load perfectly fits in to the use for electronic volume (vca) or the replacement for semi-variable resistor for tuning. features 12 bit serial data input (3 wire serial data transfer method, di, clk, ld) corresponds to ttl input for digital input (vinh 2v, vinl 0.8v) r-2r + segment method high performance 6 channel 8 bit d-a converters 6ch buffer operational amplifiers opperating in the whole voltage range from vcc to gnd buffer operational amplifiers with high oscillation stability for capacitive load application adjustment or control of industrial or home-use electronic equipments such as vtr camera, vtr set, tv, and crt display. pin configuration(top view) outline 16p2e-a 1 clk 2 di 3 v dd 5 7 8 vss 6 4 a o 1 a o 2 nc 16 14 12 10 9 11 13 ld 15 nc a o 3 a o 5 a o 4 a o 6 v cc d o gnd (vrefu) (vrefl) d1110 9 8 d7 6 5 4 3 2 1 0 d-a l ch1 d-a 3 l 4 (6) d-a d-a l l 5 ch6 2 ao6 ao5 ao4 ao3 v ss v dd v cc (6) 16 15 14 13 12 11 9 do ld clk di ao1 ao2 gnd 1 2 3 4 5 6 8 8bit r-2r segment d-a converter 8bit r-2r segment d-a converter
( / 6) mitsubishi 0107 M62354AGP 8bit 6ch d-a converter with buffer amplifiers 2 explanation of terminals symbol di serial data input terminal. 12 bit serial data is input to this terminal. clk serial clock input terminal. input signal from di terminal is input to 12 bit shift register upon the rise of shift clock 8bit d-a converter output terminal. power supply terminal. digital and analog common gnd function pin no. do serial data output terminal. serial data of 12 bit shift register is output from this terminal. ld ao1 ao2 ao3 ao4 ao5 ao6 v cc gnd v dd d-a converter high level reference voltage input terminal. 1 9 4 15 5 6 11 12 13 14 16 2 3 8 block diagram for explanation of terminals 8bit latch (6) di v cc gnd v dd decoder ao1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 12 bit shift register clk ld a1 do 5 1 8 15 16 4 2 3 8bit latch a6 14 ao6 1 2 3 4 5 6 v ss (8) v ss d-a converter low level reference voltage input terminal. d0 d7 d0 d7 9 data is loaded to register when 'h' is input to ld terminal. built-in buffer amp. is connected to vcc. d-a converted voltage between vdd and vss is output to each terminal. 8bit r-2r + segment d-a converter 8bit r-2r + segment d-a converter
( / 6) mitsubishi 0107 M62354AGP 8bit 6ch d-a converter with buffer amplifiers 3 digital data format dac select data d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dac select data dac data msb lsb dac data 0 0 0 0 1 0 0 0 0 1 0 0 d4 d5 d6 d7 d0 d1 d2 d3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (vrefu-vrefl)/256x1+vrefl[v] (vrefu-vrefl)/256x2+vrefl[v] (vrefu-vrefl)/256x3+vrefl[v] (vrefu - vrefl) / 256 x 255+vrefl[v] vrefu[v] d-a output (256lsb) (255lsb) (3lsb) (2lsb) (1lsb) vrefu=v dd vrefl=v ss 1 : : : : : : : : : 1 0 0 0 0 1 0 (vrefu-vrefl)/256x4+vrefl[v] (3lsb) first last 1 1 1 1 don't care 0 0 0 1 a01select 0 0 1 0 a02select 0 0 1 1 a03select 0 1 0 0 a04select 0 1 0 1 a05select 0 1 1 0 a06select 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 don't care 1 1 1 0 don't care d11 d10 d9 d8 dac selection 0 0 0 0 don't care ld clk si ao1~ ao6 d2 d1 d0 d8 d9 d10 d11 d7 d6 d5 d4 d3 timing chart (model) don't care don't care don't care don't care don't care don't care
( / 6) mitsubishi 0107 M62354AGP 8bit 6ch d-a converter with buffer amplifiers 4 absolute maxmum rating electric characteristics symbol topr tstg d-a converter high levelreference voltage power dissipation operating temperature storage temperature parameter conditions - 0.3 ~ 7.0 - 0.3 ~ 7.0 - 20 ~ 85 - 40 ~ 125 unit v v mw ratings supply voltage vcc pd 150 vout output voltage v v digital input voltage - 0.3 ~ v cc +0.3 in v - 0.3 ~ v cc +0.3 i refu reference voltage pin current 0.7 1.3 v v ao i ao = 500a 0.1 -1.5 i ao ma differential nonlinearity nonlinearity -2.0 2.0 lsb lsb 0.2 d-a converter high level reference voltage range v dd (v refu ) buffer amplifier output drive range s dl s l szero s full co ro zero code error full scale error output capacitative load the output does not necessarily be the values within the reference voltage setting range.the output value is determined by the buffer amplifier output voltage range(vao). upper side saturation voltage=0.3v lower side saturation voltage=0.2v v refu = 4.79v without load (i ao =+0a) v refu =5v,v refl =0v,i ao =0a data condition: at maxmum current 3.5 v cc v cc -0.1 v cc -0.2 -1 -1.0 -2.0 5 1 1.0 1.5 2.0 0.1 ma v lsb lsb f ohm (vcc, vrefu=5v 10 % , vcc vrefu, gnd, vrefl=0.0v, ta= -20 ~ + 85 c unless otherwise specified.) symbol supply voltage input leak current digital input low voltage parameter conditions v in =0 ~ v cc ratings min typ max unit v v v 4.5 5.0 5.5 a digital input high voltage v ol digital output low voltage i ol = 2.5ma v -10 10 0.4 vcc icc supply current clk=1mhz operation 2.5 0.8 2.0 ma v oh digital output high voltage i oh = - 400a v v cc -0.4 v cc =5 v, i ao =0a 0.7 v refl = 0.95v (15mv/lsb) v cc = 5.5v v ss (v refl ) gnd v cc - 3.5 d-a converter low level reference voltage range i ao = 100a c c symbol parameter conditions ratings min typ max unit buffer amplifier output drive range vdd vil iilk vih buffer amp. output impedance note2: typical value is for ta=25 c note3: changes from m62354gp: digital input voltage corresponds to ttl spae. (vcc, vrefu=5v 10 % , vcc vrefu, gnd, vrefl=0.0v, ta= -20 ~ + 85 c unless otherwise specified.)
( / 6) mitsubishi 0107 M62354AGP 8bit 6ch d-a converter with buffer amplifiers 5 c l < 100pf input output dut timing chart symbol clock "l" pulse width data setup time data hold time parameter conditions ratings min typ max unit ld setup time 200 clock "h" pulse width clock rise time clock fall time d-a output settling time t ckl t ckh t cr t cf t dch t chl t ldd t chd the time until the output becomes the final value of 1/2 lsb 200 200 30 60 200 300 ns ns ns ns ns s ld "h"hold time t ldh 100 ns ns data output delay time t do c l 100pf ns 350 70 cl 100pf,vao:0.5 4.5v measurement circuit ld hold time t ldc 100 ns t ckl t cr t ckh t cf t dch t chd t ldh clk di ao1~ ao6 output do output t chl ld t do t chl t ldc t ldd t do = (vcc, vrefu=5v 10 % , vcc vrefu, gnd, vrefl=0.0v, ta= -20 ~ + 85 c unless otherwise specified.)
( / 6) mitsubishi 0107 M62354AGP 8bit 6ch d-a converter with buffer amplifiers 6 typical application note: M62354AGP has 3 terminals(vdd, vcc, and vss) to which constant voltage is to be applied. r ipple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. so be sure to use this device by putting cacpacitor between each terminal and gnd to get d-a conversion operation stabilized. output buffer amplifiers have high oscillation stability against capacitive load. this means that jitters by wirings around output terminals or capcitor between output and gnd(0.1uf max.) do not cause any problems with dac operations. connect capacitor(0.1uf or around) between output and gnd for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube. do clk ld di vdd(vrefu) gnd vcc 9 8 16 11 12 13 14 ao4 ao3 ao2 2 ao1 15 mcu vss(vrefl) 1 4 ao5 ao6 5 3 6
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